Electrical apparatus for adding numbers and registering the total



May 3, 1955 R. E. SPENCER ETAL 2,707,590

ELECTRICAL APPARATUS FOR ADDING NUMBERS AND REGISTERING THE TOTAL FiledMarch 20, 1951 2 Sheets-Sheet 1 CARRY DE A) ,2?

-/A/HIBI TOR V C ARRY love/2mm: ROLF EDMUND SPENCER THOMAS JULIUS REY BYm May. 3, 1955 SPENCER ETAL 2,707,590

- ELECTRICAL APPARATUS FOR ADDING NUMBERS AND REGISTERING THE TOTALFiled March 20, 1951 2 SheesSheet 2 F JANPJZ FROM 6 INVENTORS B 5 encerBY Tami; E Arrrs. Z

ELECTRICAL ArPARATus Fon ADDING NUM- snns AND REGISTERING THE TOTAL RolfEdmund Spencer, Ealing, London, and Thomas Julius Rey, Hayes, England,assignors to Electric &

Musical Industries Limited, Hayes, England, a British 3 Claims. (Cl.23561) This invention relates to electrical apparatus for adding numbersand registering the total.

It is known that the addition of numbers can be effected by a chain ofcascade-coupled thermionic valve trigger circuits, each having twostates of equilibrium, denoting the values nought and one. The triggercircuits correspond to successive binary digits and are arranged forstimulation by signals representative of a number to be added in suchmanner that a triggered device changes its state if the correspondingdigit in the binary expression for the number has the value one.Moreover, when any trigger circuit reverts to state nought from stateone it transmits a pulse representative of a carry which (except in thecase of the last circuit of the chain) causes the succeeding triggercircuit to undergo a change of state. The state of the chain thus givesa binary indica tion of the total of numbers which have been previouslyadded but since the chain operates inherently on a binary scale, it isdifficult for the total registered to be dislayed in decimal notation,which is often desirable.

It has also been proposed in the R. C. A. Review of September 1946, page441 et seq., to provide electrical counting apparatus which when fedsuccessively with pulses representative of unity displays the totalnumber of applied pulses in decimal notation. The proposed ap paratusoperates on a mixed system of radices, known as the bi-quinary system,and for each decimal digit displayed there is a chain of three triggeredcircuits for setting up a quinary digit and a further trigger circuitfor converting the quinary digit to a decimal digit. Each chain of threecircuits has eight possible states but only five are required and so itis arranged that three of the states are prevented from arising, thesestates being said to be forbidden.

Considerable advantage could be obtained if the apparatus according tothe latter proposal were capable of addition, that is if numbers notonly equal to but greater than unity could be added to a previouslyregistered number, as distinct from mere counting, that is finding thesuccessor to a previously registered number, but difliculty isencountered due to the aforementioned forbidden states.

The object of the present invention is to reduce such difiiculty.

According to the present invention, there is provided apparatus foradding numbers and registering the total in a scale of radix M,comprising n trigger devices each having two states of equilibriumbetween which the devices can be caused to alternate on the applicationof triggering pulses, means coupling said devices in cascade to producea series counter chain having 2 states, n being such that 2 is greaterthan M and the values 0 to M-l being assigned to M states of said chain,means for applying triggering pulses individually to the devices in saidchain so that the addition of numbers equal to or greater than unity canbe represented, the coupling means being so arranged that on theapplication of pulses representing a number less than M the chaininitially changes to the correspondingly higher one of said 2 UnitedStates Patent C states and means are provided so arranged that, when theinitial changes produce a state other than that whose assigned valuerepresents the resultant total, a further change is produced to thelast-mentioned state.

It is to be understood that, in apparatus according to the presentinvention, it will be necessary to take account of changes of the chainrepresenting a carry to the next higher digital place in the scale ofradix M, and when by operation of the last-mentioned means a changeoccurs from a state whose binary indication is higher than M, the stateof the chain after the change will be that whose assigned valuerepresents the resultant total taking account of the carry. It will alsobe appreciated that numbers having more than one digit in the scale ofradix M can be handled by repeating the apparatus required to handle asingle digit the appropriate number of times, suitable provision beingmade for dealing with carry signals.

In the preferred form of apparatus according to the present invention,the values 0 to (M1) are assigned respectively to the states of thechain whose binary indications are the same as the assigned numbers, andsaid last-mentioned means are so arranged that when the devices arechanged to one of the remaining states or to 'a state which is reachedby crossing the remaining states, a signal representative of (Z -M) isautomatically applied to said devices.

In the application of the preferred form of the invention to apparatusin which there are three triggered devices in a chain as in the countingapparatus previously referred to, 2 would equal 8, M would equal 5 andthe remaining, or so called forbidden, states would correspond to thenumbers 5, 6 and 7.

Crossing the forbidden states implies the antecedent addition to analready registered number of another number such that the answer equalsor exceeds 2 that is if four is added to the chain when it alreadyregisters four in the case of the above-mentioned chain of threedevices.

In order that the said invention may be clearly understood and readilycarried into effect, the same will now be more fully described withreference to the drawings in which:

Figure 1 illustrates symbolically, utilizing what is re ferred to aslogical symbolism, one example of apparatus according to the presentinvention,

Figure 2 illustrates a modification of Figure 1,

Figure 3 illustrates a form of triggered circuit suitable for use in theapparatus of Figures 1 and 2,

Figure 4 illustrates a form of gate having threshold 1 suitable for usein the appaartus of Figures 1 and 2, and

Figure 5 illustrates a form of gate having threshold 2 suitable for usein the appaartus of Figures 1 and 2.

The logical symbols utilized in the drawings are de scribed in chapter 8of Calculating Instruments and Machines by D. R. Hartree, published bythe University of Illinois Press.

Referring to Figure 1, the units 11), 11 and 12 represent triggeredcircuits of the Eccles-Iordan type having two stable states ofequilibrium, each circuit changing from one state to the other each timea pulse is received at its input. For example, the circuits 10, 11 and12, except as regards the application of input pulses and the feedbackconnections which will be referred to subsequently, may be arranged asdescribed with reference to Figure 6 in the article entitled ElectronicCounters in the R. C. A. Review of September 1946, page 438. Thecircuits 10, 11 and 12 are arranged to receive informationrepresentative of numbers, of single digital significance in the scaleof five. The received information is fed in binary code by means ofconnections 13, 14 and 15 to the circuits 10, 11 and 12 which correspondrespectively to 2, 2 and 2 digits a pulse being fed to the respectivecircuit each time it is required to register a number in which thecorresponding binary digit has the value 1. No pulse is received if thecorresponding binary digit has the corersponding value nought. One ofthe two states of each of the circuits 10, 11 and 12 is referred to asthe state nought and the other state as the state one and the endelements 16, 17 and 18 indicate that each of the circuits 10, 11 and 12feeds out a potential excursion each time it reverts to its statenought. It will be appreciated that, with the arrangement disclosed inthe R. C. A. Review aforesaid, the end elements have no separateidentity, the feeding out of potential excursions with each reversion ofthe trigger circuit to state being an inherent property of triggercircuits of the Eccles-Iiordan type. The potential excursions from theend elements 16 and 17 are fed respectively to the circuits 11 and 12 asshown while the potential excursion from the cnd element 18 is, it willbe assumed, fed to a further chain of triggered circuits which registerthe digit of next higher order. The highest input which, on operation ofthe circuit, will be fed to the circuits 10, 11 and 12 by theconnections 16, 17 and 18 is four, or 001 in the binary scale where thebinary expression is written so that digital order increases from leftto right, and when any number from one to four is fed to the circuits10, 11 and 12, these circuits undergo a change of state to thecorresponding higher one of the eight states of the chain representingthe addition of the respective number. The circuits can indicate valuesfrom nought to seven but since they are required to form a quinaryregister, values are assigned only to the states nought to four and thestates five, six and seven are made forbidden states in a manner whichwill hereinafter appear. Moreover it will be assumed that the circuits10, 11 and 12 are preceded by a further trigger circuit whereby theregister is arranged to operate in accordance with the decimal scale ofnotation. However, for simplicity of description, the circuit will bedescribed as operating according to a scale of five.

Connections 19 and 2% are provided from the outputs of the circuits and11 to a gate 21 which feeds out a pulse if a pulse is received fromeither of the circuits 10 or 11 or both, that is the gate 21 has thethreshold 1. This type of gate is commonly called an or gate. The outputpulse from the gate 21 is fed to a gate 22 of threshold two, morecommonly known in the U. S. as an and gate, the output of circuit 12being also fed to the gate 22. If the gate 22 is stimulated, it feedsout a pulse in parallel to the inputs of the circuits 10 and 11, thusautomatically adding three (110 in the binary scale) to the numberregistered by the chain of circuits. The addition of three by thestimulation of the gate 22 thus occurs if any of the (decimal) numbersfive, six or seven is registered by the apparatus, and the register thenchanges automatically to the states representative of nought, one ortwo, respectively and the circuit 12 reverts to state nought feeding outa carry from 18, representative of five.

By virtue of a connection 23 through a gate 24 of threshold one with aninhibitor input terminal connected to the output of the gate 22, theoccurrence of a carry from the end element 18 also causes three to befed back in the form of pulses at the input of the circuits 10 and 11,unless inhibited by the stimulation of the gate 22. The gate 22 isconnected to the inhibitor by a delay device 25 which ensures that theinhibition is delayed until the initial changes in response to pulsesapplied via 13, 14 and 15 have occurred, that is the inhibition iseffective only if the carry is a direct result of the stimulation of 22,no further feedback being then permitted. In the present example such asituation can arise only if four is added when the circuits 10, 11 and12 are already registering four (i. e. 001). The circuit 12 then revertsto state nought the end element 18 feeds out a carry, (that is theforbidden states five, six and seven have been crossed but notestablished) and three is added by feedback. The circuits 10, 11 and 12finally register (+carry), namely eight taking account of the carry.Thus, the principle of operation of the example described is that if, asa result of the addition of a number, the chain changed directly to astate one, two, three or four, no further change is effected as aconsequence of the addition. If on the other hand, the addition of anumber other than zero changes the chain to a state whose binaryindication is five, six, seven or nought, the chain automaticallychanges to the state whose indication is the transient binary indicationless 5. It will be appreciated that the states whose binary indicationsare five, six and seven are forbidden states to which no quinary digitvalue is assigned, while state nought reached by crossing the forbiddenstates as the result of an addition, is a binary indication of eightwhich is different from the assigned quinary digit value. If the chainundergoes a transition to a forbidden state, or across the forbiddenstates, the gates 21 and 22, or 24, as the case may be, function ascount-advancing means to cause the chain to register the total as adigit of radix 5, and the connection from 22 to 24 via 25 functions asmeans for inhibiting the gate 24 in response to stimulation of the gate22.

In order to illustrate the operation of the apparatus, it will beassumed that three is registered and four is added.

The following sequence occurs:

1 1 0 three is registered 0 0 1 four is assumed to be added; 1 l l, i.e. seven is set up, hence the gate 22 Instead of connecting the gate 22to the inhibitor of the gate 24, the same result can be achieved byconnecting the gate 21 to the inhibitor of the gate 24, by a delaydevice. According to another modification, the inhibitor 24 is omittedentirely so that a carry from 18 will in every case tend automaticallyto add in three by feedback. However, it is arranged that the feedbackpath has such a recovery time that if the carry is a direct result ofthe stimulation of the feedback path, the carry is fed out of 18 beforethe feedback path has recovered to a condition in which it is capable offurther stimulation.

The modification illustrated in Figure 2 is generally similar to theapparatus illustrated in Figure 1 except that feedback from the endelement 18 is replaced by feedback to the gate 22 from the inputconnection 15 of the triggered circuit 12 through gate 27 having aninhibitor connection from the gate 21. The gate 22 is then stimulatedwhen a forbidden state arises, that is when circuit 12 is in state oneand either 10 or 11 or both are in state one, and it is also stimulatedwhen the circuit 12 is in state one and four (001) is added. A delaydevice 28 allows for the finite settling time of the triggered circuits.

Other arrangements for carrying the invention into effect are alsopossible. For example, to allow for crossing a forbidden state aseparate gate of threshold 2 could be provided arranged to feed in threewhen a carry is fed out of the end element 18, if a pulse has just beenfed to the input of the triggered circuit 12. This can be achieved bymaking connections to the last-mentioned gate from the end element 18and, via a delay device, from the input connection 15. When, asabove-mentioned, the triggered circuits 10, 11 and 12 are preceded by afurther triggered circuit, a delay longer than the time of settling ofthe chain 10, 11 and 12 must be provided between the preceding circuitand the chain, so that an incoming carry will always find the chain in apermitted state. A similar consideration applies to each stage ofapparatus following the chain 10, 11 and 12. The additional triggercircuit for translating the register of the chain 10, 11 and 12 to adecimal digit may, if desired, follow the chain instead of precedingit.

The triggered circuit shown in Figure 3 can be used as any of thetriggered circuits shown in Figures 1 and 2, and it also performs thefunction of the corresponding end element. In Figure 3, the circuitshown is assumed to represent the structural form of the elements 11 17,and it is also of the form illustrated in Figure 6, page 442 of the RQAReview, September 1946. The circuit comprises two valves 30 and 31having their anodes and their control electrodes cross-coupled byresistance 32 to 38 and by capacitors 39 and 4%). The input from theproceeding triggered circuit is applied to the lower end of resistor 32via capacitor 41, and the output is taken from the anode of the valve31. Feedback to the circuit is applied to the control electrode of thevalve 31 via capacitor 42 and resistor 43. Input signals on the lead 14can be applied in the same way as the feedback, namely via capacitor 44and resistor 45.

The gate shown in Figure 4, which may be used for the gate 21, comprisesvalve 46 whose control electrode is negatively biassed beyond cut-offvia resistor 4'7. Signals taken from any suitable point are applied viadiodes 48 and 49 connected as shown to the control electrode of valve46. The input either from the circuit or the circuit 11 switches on thevalve 46 and sets up an output signal at the anode of that valve. Thegate shown in Figure 4 is of the construction illustrated in Figure 2(H), page 112 of Electronics, September 1948.

The gate of threshold 2 illustrated in Figure 5, which can be used forthe gate 22, comprises a hexode valve 50 having both control electrodesnormally biassed beyond cutoff, so that an output can be set up at theanode only when input signals are applied simultaneously to the innerand outer control electrodes respectively. The gate shown in Figure 5 isof the construction illustrated in Figure 2 (A), page 112 ofElectronics, September 1948.

The gate 24 can be of the same construction as that shown in Figure 5,arranged in such a way that the application of a signal to the outercontrol electrode will cause the valve 50 to conduct unless a signal issimuitaneously applied to the inner control electrode. The arrangementof a hexode valve in this way is described with reference to Figure 12,in U. S. patent specification No. 2,224,134 in the name of A. D.Blumlein.

The delay devices and 28 may be of conventional construction such aswidely used in the radio art.

The invention is not restricted to applications in which the valuesnought to four (assuming a quinary register) are assigned to thosestates whose binary indications are the same as the assigned numbers.For example, the values nought to four may be assigned to those stateswhose binary indications are, respectively, nought, one, two, three, andsix. The forbidden states are not then consecutive and the principle ofoperation is such that if the state four or five obtains or is crossed,two is added automatically, if state seven obtains or is crossed, unityis added in automatically.

It will be appreciated that other variations are possible.

What we claim is:

1. Electrical apparatus for adding numbers of single digitalsignificance in a scale of radix M and registering the total, where M isgreater than 2, comprising n trigger devices each having two states ofequilibrium between which the device alternates on the application ofsuccessive triggering pulses to the corresponding device, means couplingsaid devices in cascade to produce a series-counter chain having 2states of equilibrium, where n is an integer such that 2 is greater thanM, means for feeding triggering pulses to said devices individually torepresent the addition of binary digits of diiferent digitalsignificances, count-advancing means coupled to said chain andresponsive to a potential set up by a change of said chain to any one of2 M predetermined states to feed triggering pulses to a selection ofsaid trigger devices, further count advancing means coupled to saidchain and responsive to a potential set up by a change of said chainacross any of said 2 M states to feed triggering pulses to a selectionof said triggering devices, and means responsive to operation of saidfirst count advancing means for inhibiting said further count advancingmeans, said count advancing means being predetermined to register thecount in said chain as a digit of radix M.

2. Electrical apparatus for adding numbers of single digitalsignificance in a scale of radix 5 and registering the total, comprisingthree trigger devices each having two states of equilibrium betweenwhich the device alternates on the application of successive triggeringpulses to the corresponding device, means coupling said devices incascade to produce a series-counter chain having eight states ofequilibrium, means for feeding triggering pulses to said devicesindividually to represent the addition of binary digits of differentdigital significances, count-advancing means coupled to said chain andresponsive to a potential set up by a change of said chain to any one ofthree successive states to feed pulses representative of 3 to saidtrigger devices, further count-advancing means coupled to said chain andresponsive to a potential set up by a change of said chain across saidthree successive states to feed pulses representative of 3 to saidtrigger devices, and means responsive to operation of said firstcount-advancing means for inhibiting said further countadvancing means,whereby said chain registers the totals as a digit of radix 5.

3. Electrical apparatus for adding numbers of single digitalsignificance in a scale of radix 5 and registering the total, comprisingthree trigger devices each having two states of equilibriumrepresentative respectively of 0 and 1 and between which the devicealternates on the application of successive triggering pulses to thecorrespending device, means coupling said devices in cascade to producea series-counter chain having eight states of equilibrium, means forfeeding triggering pulses to said devices individually to represent theaddition of binary digits of different digital significances, countadvancing means coupled to each of said devices and responsive to apotential set up by simultaneous changes of the third device and of oneother device in said chain to state 1 for feeding pulses representativeof 3 to said trigger devices, further count-advancing means coupled tosaid third device and responsive to a potential set up by a change ofsaid third device ta state 0 for feeding a signal representative of 3 tosaid trigger devices, and means responsive to operation of said firstcount-advancing means for inhibiting said further count-advancing means,whereby said chain is caused to register totals as a digit of radix 5.

References Cited in the file of this patent UNITED STATES PATENTS

